Espressif Systems /ESP32-C3 /DMA /INT_RAW_CH1

The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.

The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.

The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.

The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.

The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.

The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.

The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.

The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.

The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.

This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.

This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.

This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.

This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.